1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a semiconductor wafer suitable for integration of a circuit arrangement for power IC devices which include high-voltage transistors.
2. Description of the Related Art
Power semiconductor devices, such as bipolar transistors and metal-oxide semiconductor field effect transistors (MOSFETs), are generally connected in series with each other in an inverter circuit or the like. In such a circuit, diodes are often connected in parallel with series-connected transistors, respectively. In fact, many semiconductor IC manufacturers have produced circuit modules in which transistors connected in series with each other in this manner and diodes connected in parallel therewith are packaged into a single chip.
One circuit using such circuit modules is a three-phase inverter circuit, which includes the above-mentioned series-transistor/parallel diode circuit module and gate circuits for driving and controlling the module. Typically, such an inverter circuit includes three sets of series-circuits of transistors, each set consisting of a couple of bipolar transistors that are connected in series with each other. Six diodes are respectively connected in parallel with these bipolar transistors. Each of these transistors is provided with a gate circuit for driving it. The three sets of transistor circuits have two common connection terminals, one of which serves as a power supply voltage terminal, and the other of which acts as a ground terminal.
With such an arrangement, when the six gate circuits are to be integrated together onto one chip, optimal region separation cannot be performed due to the differences in the electrical operating environment among different gate circuit modules on the same wafer substrate. This problem is a serious factor which delays realizing IC packaging of high-voltage circuits for power semiconductor devices, which have been strongly demanded for a long time. The differences in the electrical operating environment may be caused in a case wherein a certain one of the gate circuits having the same element structure is constantly biased by a higher voltage, or a case wherein the reference voltage to a specific one of the gate circuits greatly varies within the range of a power source voltage to a ground potential depending on the operating states of another adjacent circuit.
Presently available dielectric isolation techniques may be used to perform the "individual independence region separation" on the same wafer substrate, i.e., in order to electrically separate a certain gate circuit module region from the remaining ones so as to allow it to operate independently of the operating states of the remaining ones. However, a wafer substrate having the dielectric separation structure suffers from several drawbacks, i.e., a complicated manufacturing process, limited integration, and high cost. These drawbacks make semiconductor manufacturers hesitate to apply the dielectric separation structure to the integration of high-voltage transistors and peripheral circuits If different operating environments of the respective gate circuits are compensated by techniques in circuit design, an overall circuit arrangement is undesirably complicated.